A logic-simulation model of a device is a diagnostic tool which accurately mimics digital logic and timing behavior of a device in normal operation. The purpose of such a model is to verify both logic and timing of an operational digital system containing the device. In a logic-simulation model, internal operation and internal structure need not be similar to that of the actual device being simulated. The only prerequisite is that the simulated operation and simulated timing as externally observed be identical to that of the actual device being modeled.
Traditionally, logic-simulation models have been implemented with software. Software logic-simulation models have been of two types, namely structural models and behavioral models. A structural model mimics actual internal logical structure of a device from which observable functional behavior follows. A behavioral model merely mimics external logical and timing behavior.
Software models of complex devices have numerous disadvantages. First, they are relatively costly and time consuming to develop. To design an accurate model, specifications of the device must be gathered and thoroughly understood. This has been a serious limitation because manufacturers of devices are generally reluctant to disclose such details. Moreover, the specifications required for modeling a device are typically much more detailed than those relevant to a typical user of the device.
Second, software simulation models are characteristically slow because of the amount of computation required to simulate device functions. Typically, the amount of computation required to simulate external components in a full system being modeled is negligible compared with the amount of computation required for the complex device itself. In fact, software logic simulation models are frequently too slow to be of practical utility.
As complex devices become more dense, the problems of simulation, including development cost, model accuracy, and the requirements to simulate at high speed can be expected to become acute. U.S. Pat. Nos. 4,590,581 and 4,635,218 issued in the name of C. L. Widdoes discloses a method and apparatus for modeling systems of complex circuits and a method for simulating system operation of static and dynamic circuit devices, respectively.
U.S. Pat. No. 4,590,581 discloses a model which comprises a combination of a physical device to be modeled and means for controlling the physical device at normal operating speeds so as to avoid loss of data or of accumulated functions. Specifically, the physical device to be modeled is connected through a micro-system simulation means which can accept any of a wide variety of external devices and which includes the logic circuitry and control means necessary to allow the physical device to be stimulated and the resulting behavior observed under external control. Data and logic state patterns are preserved by effective control of the starting, stopping, cycling and resetting of the physical device. A known good physical sample of the device being modeled, for example a dynamic digital circuit, such as a microprocessor circuit is employed in connection to a digital system to be tested, the system including other digital circuits to be tested in the environment of the system. The physical sample, referred to as the reference element, is coupled through a device referred to as a personality module to a device called a simulation jig. The purpose of the personality module is to provide the electrical and physical configurations for interfacing the specific reference element with the simulation jig. The simulation jig is coupled to a computer controlled system designated a logic-simulator to provide appropriate input signals and to sample the resulting output signals in such a way that the user need not be aware that the reference element is either a software or a hardware model. In fact, a user of a simulation library may mix devices having software models with devices having physical models without concern about type.
In a specific implementation of Widdoes' invention, a first input pattern is precomputed and stored in a fast memory. An input pattern is the parallel pattern of bits presented during an interval of time (e.g., at a clock edge) to the reference element. Before the reference element is initially exercised it is first reset or restored to a preselected condition which can be identically restored at any future time. The first or initial input pattern termed the first "sequence" is typically fetched from the fast memory and presented to input terminals of the reference element to cause the reference element to respond to produce an output pattern. The output values resulting from the first input pattern are termed the first output pattern. Thereafter, the resultant first output pattern of the reference element is recorded. Using the first output pattern, the logic simulator computes a second input pattern which is then stored in the fast memory along with the first input pattern, thereby creating a second sequence. The second sequence thus consists of the first and second input patterns. The reference element is reset to prepare to receive the second sequence. Thereafter the second sequence is played back to the reference element by sequentially presenting to the reference element the first two input patterns at a preselected rate. After the end of the second sequence of input patterns has been played back to the reference element, the second output pattern of output values of the reference element is sampled. Employing the resultant output pattern, the logic simulator may compute off-line the next input pattern, store this computed input pattern at the end of the sequence of input patterns previously stored, reset the reference element, either by activating a reset signal line or by applying a reset pattern sequence to the reference element and then repeat the sequence of input patterns such that the next operational sequence produces one additional input pattern.
The logic simulator iteratively advances the state of the reference element by starting each sequence of iterations from a reference state designated the reset state.
Although Widdoes provides the capability of presenting the reference element with a reset sequence, there is no capability of presenting an off-circuit sequence which will produce a desired off-circuit behavior in the reference element. For example, if a specific sequence were presented to the reference element evoking a read operation of a register within the reference element, the sequence would modify normal activity in the simulated circuit. Indeed if such a sequence were appended to the previously accumulated input patterns as taught in the prior art, pattern memory would be altered; any subsequent pattern replay would include the replay of the specific read sequence and thus alter the natural flow of circuit events.
It is therefore an object of the invention to provide the capability of causing the system to generate desired off-circuit results during a simulation without affecting the natural behavior of the circuit being simulated.